From c1607b54ff8e77ffcb0ee1a89ebad16e2cb06b8d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Aug 2009 11:49:00 +0200 Subject: [PATCH] OV96xx soc camera driver --- arch/arm/mach-pxa/include/mach/palmz72.h | 5 + arch/arm/mach-pxa/palmz72.c | 127 ++++++- drivers/media/video/Kconfig | 6 + drivers/media/video/Makefile | 1 + drivers/media/video/ov96xx.c | 676 ++++++++++++++++++++++++++++++ include/media/ov96xx.h | 392 +++++++++++++++++ include/media/v4l2-chip-ident.h | 2 + 7 files changed, 1208 insertions(+), 1 deletions(-) create mode 100644 drivers/media/video/ov96xx.c create mode 100644 include/media/ov96xx.h diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 2806ef6..745fa3c 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h @@ -44,6 +44,11 @@ #define GPIO_NR_PALMZ72_BT_POWER 17 #define GPIO_NR_PALMZ72_BT_RESET 83 +/* Camera */ +#define GPIO_NR_PALMZ72_CAM_PWDN 56 +#define GPIO_NR_PALMZ72_CAM_RESET 57 +#define GPIO_NR_PALMZ72_CAM_POWER 91 + /** Initial values **/ /* Battery */ diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 9f9b956..af133df 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -44,8 +45,10 @@ #include #include #include - #include +#include + +#include #include "generic.h" #include "devices.h" @@ -120,6 +123,29 @@ static unsigned long palmz72_pin_config[] __initdata = { GPIO22_GPIO, /* LCD border color */ GPIO96_GPIO, /* lcd power */ + /* PXA Camera */ + GPIO81_CIF_DD_0, + GPIO48_CIF_DD_5, + GPIO50_CIF_DD_3, + GPIO51_CIF_DD_2, + GPIO52_CIF_DD_4, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO55_CIF_DD_1, + GPIO84_CIF_FV, + GPIO85_CIF_LV, + GPIO93_CIF_DD_6, + GPIO108_CIF_DD_7, + + GPIO56_GPIO, + GPIO57_GPIO, + GPIO91_GPIO, + GPIO99_GPIO, + + /* I2C */ + GPIO117_GPIO, /* I2C_SCL */ + GPIO118_GPIO, /* I2C_SDA */ + /* Misc. */ GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */ GPIO88_GPIO, /* green led */ @@ -398,6 +424,70 @@ static struct pxafb_mach_info palmz72_lcd_screen = { .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, }; +/****************************************************************************** + * SoC Camera + ******************************************************************************/ +struct pxacamera_platform_data palmz72_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 2600, +}; + +/* Board I2C devices. */ +static struct i2c_board_info __initdata palmz72_i2c_device = { + I2C_BOARD_INFO("ov96xx", 0x30), +}; + +static int palmz72_camera_power(struct device *dev, int power) +{ + gpio_set_value(GPIO_NR_PALMZ72_CAM_PWDN, !power); + mdelay(50); + return 0; +} + +static int palmz72_camera_reset(struct device *dev) +{ + gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 1); + mdelay(50); + gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 0); + mdelay(50); + return 0; +} + +static struct soc_camera_link palmz72_iclink = { + .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */ + .board_info = &palmz72_i2c_device, + .i2c_adapter_id = 0, + .module_name = "ov96xx", + .power = &palmz72_camera_power, + .reset = &palmz72_camera_reset, + .flags = SOCAM_DATAWIDTH_8, +}; + +static struct i2c_gpio_platform_data palmz72_i2c_bus_data = { + .sda_pin = 118, + .scl_pin = 117, + .udelay = 10, + .timeout = 100, +}; + +static struct platform_device palmz72_i2c_bus_device = { + .name = "i2c-gpio", + .id = 0, /* we use this as a replacement for i2c-pxa */ + .dev = { + .platform_data = &palmz72_i2c_bus_data, + } +}; + +struct platform_device palmz72_camera = { + .name = "soc-camera-pdrv", + .id = -1, + .dev = { + .platform_data = &palmz72_iclink, + }, +}; + + #ifdef CONFIG_PM /* We have some black magic here @@ -481,6 +571,8 @@ static struct platform_device *devices[] __initdata = { &palmz72_asoc, &power_supply, &palmz72_gpio_vbus, + &palmz72_i2c_bus_device, + &palmz72_camera, }; /* setup udc GPIOs initial state */ @@ -492,10 +584,41 @@ static void __init palmz72_udc_init(void) } } +/* Here we request the camera GPIOs and configure them. We power up the camera + * module, deassert the reset pin, but put it into powerdown (low to no power + * consumption) mode. This allows up later to bring the module up fast. */ +static inline void __init palmz72_cam_init(void) +{ + if (gpio_request(GPIO_NR_PALMZ72_CAM_PWDN, "Camera PWDN")) + goto err1; + if (gpio_request(GPIO_NR_PALMZ72_CAM_RESET, "Camera RESET")) + goto err2; + if (gpio_request(GPIO_NR_PALMZ72_CAM_POWER, "Camera DVDD")) + goto err3; + if (gpio_direction_output(GPIO_NR_PALMZ72_CAM_POWER, 1)) + goto err4; + if (gpio_direction_output(GPIO_NR_PALMZ72_CAM_RESET, 0)) + goto err4; + if (gpio_direction_output(GPIO_NR_PALMZ72_CAM_PWDN, 0)) + goto err4; + return; + +err4: + gpio_free(GPIO_NR_PALMZ72_CAM_POWER); +err3: + gpio_free(GPIO_NR_PALMZ72_CAM_RESET); +err2: + gpio_free(GPIO_NR_PALMZ72_CAM_PWDN); +err1: + printk("Camera GPIO init failed!\n"); + return; +} + static void __init palmz72_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); + palmz72_cam_init(); set_pxa_fb_info(&palmz72_lcd_screen); pxa_set_mci_info(&palmz72_mci_platform_data); palmz72_udc_init(); @@ -503,6 +626,8 @@ static void __init palmz72_init(void) pxa_set_ficp_info(&palmz72_ficp_platform_data); pxa_set_keypad_info(&palmz72_keypad_platform_data); + pxa_set_camera_info(&palmz72_pxacamera_platform_data); + platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index 061e147..2940b84 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -764,6 +764,12 @@ config SOC_CAMERA_OV772X help This is a ov772x camera driver +config SOC_CAMERA_OV96XX + tristate "ov96xx camera support" + depends on SOC_CAMERA && I2C + help + This is a ov96xx camera driver + config MX1_VIDEO bool diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index 7fb3add..74333c4 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031.o obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o obj-$(CONFIG_SOC_CAMERA_OV772X) += ov772x.o +obj-$(CONFIG_SOC_CAMERA_OV96XX) += ov96xx.o obj-$(CONFIG_SOC_CAMERA_TW9910) += tw9910.o # And now the v4l2 drivers: diff --git a/drivers/media/video/ov96xx.c b/drivers/media/video/ov96xx.c new file mode 100644 index 0000000..67b8eb5 --- /dev/null +++ b/drivers/media/video/ov96xx.c @@ -0,0 +1,676 @@ +/* + * OmniVision OV96xx Camera Driver + * + * Copyright (C) 2009 Marek Vasut + * + * Based on ov772x camera driver: + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Kuninori Morimoto + * + * Based on ov7670 and soc_camera_platform driver, + * + * Copyright 2006-7 Jonathan Corbet + * Copyright (C) 2008 Magnus Damm + * Copyright (C) 2008, Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* read a register */ +static int ov96xx_reg_read(struct i2c_client *client, u8 reg, u8 *val) +{ + int ret; + u8 data = reg; + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = &data, + }; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) + goto err; + + msg.flags = I2C_M_RD; + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) + goto err; + + *val = data; + return 0; + +err: + dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); + return ret; +} + +/* write a register */ +static int ov96xx_reg_write(struct i2c_client *client, u8 reg, u8 val) +{ + int ret; + u8 _val; + unsigned char data[2] = { reg, val }; + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + .len = 2, + .buf = data, + }; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) { + dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); + return ret; + } + + /* we have to read the register back ... no idea why, maybe HW bug */ + ret = ov96xx_reg_read(client, reg, &_val); + if (ret) + dev_err(&client->dev, "Failed reading back register " + "0x%02x!\n", reg); + + return 0; +} + + +/* Read a register, alter it's bits, write it back */ +static int ov96xx_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset) +{ + /*s32*/u8 val; + int ret; + + ret = ov96xx_reg_read(client, reg, &val); + if (ret) { + dev_err(&client->dev, "[Read]-Modify-Write of register %02x" + " failed!\n", reg); + return val; + } + + val |= set; + val &= ~unset; + + ret = ov96xx_reg_write(client, reg, val); + if (ret) + dev_err(&client->dev, "Read-Modify-[Write] of register %02x" + "failed!\n", reg); + + return ret; +} + +/* Soft reset the camera. This has nothing to do with the RESET pin! */ +static int ov96xx_reset(struct i2c_client *client) +{ + int ret; + + ret = ov96xx_reg_write(client, OV96XX_COM7, OV96XX_COM7_SCCB_RESET); + if (ret) + dev_err(&client->dev, "An error occured while entering " + "soft reset!\n"); + + return ret; +} + +/* Start the camera (power it up, hardware reset it) */ +static int ov96xx_init(struct soc_camera_device *icd) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + int ret = 0; + + if (priv->link->power) { + ret = priv->link->power(&priv->client->dev, 1); + if (ret < 0) { + dev_err(&priv->client->dev, "An error occured while " + "powering up the device!\n"); + goto err; + } + } + + if (priv->link->reset) { + ret = priv->link->reset(&priv->client->dev); + if (ret) { + dev_err(&priv->client->dev, "An error occured while " + "reseting up the device!\n"); + goto err2; + } + } + + return 0; + +err2: + ret = priv->link->power(&priv->client->dev, 0); + if (ret) + dev_err(&priv->client->dev, "An error occured while powering " + "down the device!\n"); +err: + return ret; +} + +/* Power down the camera. */ +static int ov96xx_release(struct soc_camera_device *icd) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + int ret = 0; + + if (priv->link->power) { + ret = priv->link->power(&priv->client->dev, 0); + if (ret) + dev_err(&priv->client->dev, "An error occured while powering " + "down the device!\n"); + } + + return ret; +} + +/* Start capturing (inline since it does nothing) */ +static int ov96xx_start_capture(struct soc_camera_device *icd) +{ + return 0; +} + +/* Stop capturing (inline since it does nothing) */ +static inline int ov96xx_stop_capture(struct soc_camera_device *icd) +{ + return 0; +} + +/* Alter bus settings on camera side (inline since it does nothing) */ +static inline int ov96xx_set_bus_param(struct soc_camera_device *icd, + unsigned long flags) +{ + return 0; +} + +/* Request bus settings on camera side */ +static unsigned long ov96xx_query_bus_param(struct soc_camera_device *icd) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + /* + * REVISIT: the camera probably can do 10 bit transfers, but I don't + * have those pins connected on my hardware. + */ + unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8; + + return soc_camera_apply_sensor_flags(priv->link, flags); +} + +/* Get status of additional camera capabilities */ +static int ov96xx_get_control(struct soc_camera_device *icd, + struct v4l2_control *ctrl) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + ctrl->value = priv->flag_vflip; + break; + case V4L2_CID_HFLIP: + ctrl->value = priv->flag_hflip; + break; + } + return 0; +} + +/* Set status of additional camera capabilities */ +static int ov96xx_set_control(struct soc_camera_device *icd, + struct v4l2_control *ctrl) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + priv->flag_vflip = ctrl->value; + if (ctrl->value) + ret = ov96xx_reg_rmw(priv->client, OV96XX_MVFP, + OV96XX_MVFP_V, 0); + else + ret = ov96xx_reg_rmw(priv->client, OV96XX_MVFP, + 0, OV96XX_MVFP_V); + break; + case V4L2_CID_HFLIP: + priv->flag_hflip = ctrl->value; + if (ctrl->value) + ret = ov96xx_reg_rmw(priv->client, OV96XX_MVFP, + OV96XX_MVFP_H, 0); + else + ret = ov96xx_reg_rmw(priv->client, OV96XX_MVFP, + 0, OV96XX_MVFP_H); + break; + } + + return ret; +} + +/* Get chip identification */ +static int ov96xx_get_chip_id(struct soc_camera_device *icd, + struct v4l2_dbg_chip_ident *id) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + + id->ident = priv->model; + id->revision = priv->revision; + + return 0; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int ov96xx_get_register(struct soc_camera_device *icd, + struct v4l2_dbg_register *reg) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + int ret; + u8 val; + + if (reg->reg & ~0xff) + return -EINVAL; + + reg->size = 1; + + ret = ov96xx_read_reg(priv->client, reg->reg, &val); + if (ret) + return ret; + + reg->val = (__u64)val; + + return 0; +} + +static int ov96xx_set_register(struct soc_camera_device *icd, + struct v4l2_dbg_register *reg) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + + if (reg->reg & ~0xff || reg->val & ~0xff) + return -EINVAL; + + return ov9640_write_reg(priv->client, reg->reg, reg->val); +} +#endif + +/* select nearest higher resolution for capture */ +static void ov96xx_res_roundup(u32 *width, u32 *height) +{ + int i; + for (i = QQCIF; i < SXGA; i++) { + if (ov96xx_resolutions[i].width >= *width && + ov96xx_resolutions[i].height >= *height) { + *width = ov96xx_resolutions[i].width; + *height = ov96xx_resolutions[i].height; + return; + } + } + + /* BFU wants us to capture at higher resolution than we can ... + * ... 'want' is about the only thing BFU can :-) */ + *width = ov96xx_resolutions[SXGA].width; + *height = ov96xx_resolutions[SXGA].height; +} + +/* Prepare necessary register changes depending on color encoding + * (this is used at only one place, can as well be inline) */ +static inline void ov96xx_alter_regs(u32 pixfmt, struct ov96xx_reg_alt *alt) +{ + switch (pixfmt) { + case V4L2_PIX_FMT_VYUY: + alt->com12 = OV96XX_COM12_YUV_AVG; + alt->com13 = OV96XX_COM13_Y_DELAY_EN | + OV96XX_COM13_YUV_DLY(0x01); + break; + case V4L2_PIX_FMT_RGB555X: + alt->com7 = OV96XX_COM7_RGB; + alt->com13 = OV96XX_COM13_RGB_AVG; + alt->com15 = OV96XX_COM15_RGB_555; + break; + case V4L2_PIX_FMT_RGB565X: + alt->com7 = OV96XX_COM7_RGB; + alt->com13 = OV96XX_COM13_RGB_AVG; + alt->com15 = OV96XX_COM15_RGB_565; + break; + }; +} + +/* Setup registers according to resolution and color encoding + * (this is used at only one place, can as well be inline) */ +static inline int ov96xx_write_regs(struct i2c_client *client, + u32 width, u32 pixfmt, struct ov96xx_reg_alt *alts) +{ + const struct ov96xx_reg *ov96xx_regs, *matrix_regs; + int ov96xx_regs_len, matrix_regs_len; + int i, ret; + u8 val; + + /* select register configuration for given resolution */ + if (width == ov96xx_resolutions[QQCIF].width) { + ov96xx_regs = ov96xx_regs_qqcif; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_qqcif); + } else if (width == ov96xx_resolutions[QQVGA].width) { + ov96xx_regs = ov96xx_regs_qqvga; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_qqvga); + } else if (width == ov96xx_resolutions[QCIF].width) { + ov96xx_regs = ov96xx_regs_qcif; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_qcif); + } else if (width == ov96xx_resolutions[QVGA].width) { + ov96xx_regs = ov96xx_regs_qvga; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_qvga); + } else if (width == ov96xx_resolutions[CIF].width) { + ov96xx_regs = ov96xx_regs_cif; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_cif); + } else if (width == ov96xx_resolutions[VGA].width) { + ov96xx_regs = ov96xx_regs_vga; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_vga); + } else if (width == ov96xx_resolutions[SXGA].width) { + ov96xx_regs = ov96xx_regs_sxga; + ov96xx_regs_len = ARRAY_SIZE(ov96xx_regs_sxga); + } else { + dev_err(&client->dev, "Failed to select resolution!\n"); + return -EINVAL; + } + + /* select color matrix configuration for given color encoding */ + if (pixfmt == V4L2_PIX_FMT_VYUY) { + matrix_regs = ov96xx_regs_yuv; + matrix_regs_len = ARRAY_SIZE(ov96xx_regs_yuv); + } else { + matrix_regs = ov96xx_regs_rgb; + matrix_regs_len = ARRAY_SIZE(ov96xx_regs_rgb); + } + + /* write register settings into the module */ + for (i = 0; i < ov96xx_regs_len; i++) { + val = ov96xx_regs[i].val; + + if (ov96xx_regs[i].reg == OV96XX_COM7) + val |= alts->com7; + else if (ov96xx_regs[i].reg == OV96XX_COM12) + val |= alts->com12; + else if (ov96xx_regs[i].reg == OV96XX_COM13) + val |= alts->com13; + else if (ov96xx_regs[i].reg == OV96XX_COM15) + val |= alts->com15; + + ret = ov96xx_reg_write(client, ov96xx_regs[i].reg, val); + if (ret) + return ret; + } + + /* write color matrix configuration into the module */ + for (i = 0; i < matrix_regs_len; i++) { + ret = ov96xx_reg_write(client, matrix_regs[i].reg, + matrix_regs[i].val); + if (ret) + return ret; + } + + return 0; +} + +/* program default register values + * (this is used at only one place, can as well be inline) */ +static inline int ov96xx_prog_dflt(struct i2c_client *client) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(ov96xx_regs_dflt); i++) { + ret = ov96xx_reg_write(client, ov96xx_regs_dflt[i].reg, + ov96xx_regs_dflt[i].val); + if (ret) + return ret; + } + + /* wait for the changes to actually happen */ + mdelay(150); + + return 0; +} + +static inline int ov96xx_set_crop(struct soc_camera_device *icd, + struct v4l2_rect *rect) +{ + return 0; +} + +/* set the format we will capture in */ +static int ov96xx_set_fmt(struct soc_camera_device *icd, + struct v4l2_format *f) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + struct v4l2_pix_format *pix = &f->fmt.pix; + struct ov96xx_reg_alt alts = {0}; + int ret; + + ov96xx_res_roundup(&pix->width, &pix->height); + ov96xx_alter_regs(pix->pixelformat, &alts); + + ov96xx_reset(priv->client); + + ret = ov96xx_prog_dflt(priv->client); + if (ret) + return ret; + + return ov96xx_write_regs(priv->client, pix->width, + pix->pixelformat, &alts); +} + +static int ov96xx_try_fmt(struct soc_camera_device *icd, struct v4l2_format *f) +{ + struct v4l2_pix_format *pix = &f->fmt.pix; + + ov96xx_res_roundup(&pix->width, &pix->height); + pix->field = V4L2_FIELD_NONE; + + return 0; +} + +static int ov96xx_video_probe(struct soc_camera_device *icd) +{ + struct ov96xx_priv *priv = container_of(icd, struct ov96xx_priv, icd); + u8 pid, ver, midh, midl; + const char *devname; + int ret; + + /* + * We must have a parent by now. And it cannot be a wrong one. + * So this entire test is completely redundant. + */ + if (!icd->dev.parent || + to_soc_camera_host(icd->dev.parent)->nr != icd->iface) { + dev_err(&icd->dev, "Parent missing or invalid!\n"); + ret = -ENODEV; + goto err; + } + + icd->formats = ov96xx_fmt_lists; + icd->num_formats = ARRAY_SIZE(ov96xx_fmt_lists); + + /* + * check and show product ID and manufacturer ID + */ + + ret = ov96xx_reg_read(priv->client, OV96XX_PID, &pid); + if (ret) + goto err; + + ret = ov96xx_reg_read(priv->client, OV96XX_VER, &ver); + if (ret) + goto err; + + ret = ov96xx_reg_read(priv->client, OV96XX_MIDH, &midh); + if (ret) + goto err; + + ret = ov96xx_reg_read(priv->client, OV96XX_MIDL, &midl); + if (ret) + goto err; + + switch (VERSION(pid, ver)) { + case OV9640_V2: + devname = "ov9640"; + priv->model = V4L2_IDENT_OV9640; + priv->revision = 2; + case OV9640_V3: + devname = "ov9640"; + priv->model = V4L2_IDENT_OV9640; + priv->revision = 3; + break; + case OV9650: + devname = "ov9650"; + priv->model = V4L2_IDENT_OV9650; + break; + default: + dev_err(&icd->dev, "Product ID error %x:%x\n", pid, ver); + ret = -ENODEV; + goto err; + } + + dev_info(&icd->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", + devname, pid, ver, midh, midl); + + return soc_camera_video_start(icd); + +err: + return ret; +} + +static void ov96xx_video_remove(struct soc_camera_device *icd)/* OK */ +{ + soc_camera_video_stop(icd); +} + +static struct soc_camera_ops ov96xx_ops = { + .owner = THIS_MODULE, + .probe = ov96xx_video_probe, + .remove = ov96xx_video_remove, + .init = ov96xx_init, + .release = ov96xx_release, + .start_capture = ov96xx_start_capture, + .stop_capture = ov96xx_stop_capture, + .set_crop = ov96xx_set_crop, + .set_fmt = ov96xx_set_fmt, + .try_fmt = ov96xx_try_fmt, + .set_bus_param = ov96xx_set_bus_param, + .query_bus_param = ov96xx_query_bus_param, + .controls = ov96xx_controls, + .num_controls = ARRAY_SIZE(ov96xx_controls), + .get_control = ov96xx_get_control, + .set_control = ov96xx_set_control, + .get_chip_id = ov96xx_get_chip_id, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .get_register = ov96xx_get_register, + .set_register = ov96xx_set_register, +#endif +}; + +/* + * i2c_driver function + */ + +static int ov96xx_probe(struct i2c_client *client, + const struct i2c_device_id *did) +{ + struct ov96xx_priv *priv; + struct soc_camera_device *icd; + struct soc_camera_link *link = client->dev.platform_data; + struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + int ret; + + if (!link) { + dev_err(&client->dev, + "Missing platform_data from soc_camera, " + "something very wrong happened!\n"); + return -EINVAL; + } + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_err(&adapter->dev, + "I2C adapter doesn't support " + "I2C_FUNC_SMBUS_BYTE_DATA\n"); + return -EIO; + } + + priv = kzalloc(sizeof(struct ov96xx_priv), GFP_KERNEL); + if (!priv) { + dev_err(&client->dev, + "Failed to allocated memory for " + "private data!\n"); + return -ENOMEM; + } + + priv->client = client; + priv->link = link; + i2c_set_clientdata(client, priv); + + icd = &priv->icd; + icd->ops = &ov96xx_ops; + icd->control = &client->dev; + icd->width_max = ov96xx_resolutions[SXGA].width; + icd->height_max = ov96xx_resolutions[SXGA].height; + icd->iface = link->bus_id; + + ret = soc_camera_device_register(icd); + + if (ret) { + i2c_set_clientdata(client, NULL); + kfree(priv); + } + + return ret; +} + +static int ov96xx_remove(struct i2c_client *client) +{ + struct ov96xx_priv *priv = i2c_get_clientdata(client); + + soc_camera_device_unregister(&priv->icd); + i2c_set_clientdata(client, NULL); + kfree(priv); + return 0; +} + +static const struct i2c_device_id ov96xx_id[] = { + { "ov96xx", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ov96xx_id); + +static struct i2c_driver ov96xx_i2c_driver = { + .driver = { + .name = "ov96xx", + }, + .probe = ov96xx_probe, + .remove = ov96xx_remove, + .id_table = ov96xx_id, +}; + +static int __init ov96xx_module_init(void) +{ + return i2c_add_driver(&ov96xx_i2c_driver); +} + +static void __exit ov96xx_module_exit(void) +{ + i2c_del_driver(&ov96xx_i2c_driver); +} + +module_init(ov96xx_module_init); +module_exit(ov96xx_module_exit); + +MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx"); +MODULE_AUTHOR("Marek Vasut "); +MODULE_LICENSE("GPL v2"); diff --git a/include/media/ov96xx.h b/include/media/ov96xx.h new file mode 100644 index 0000000..7f4f58f --- /dev/null +++ b/include/media/ov96xx.h @@ -0,0 +1,392 @@ +/* + * OmniVision OV96xx Camera Header File + * + * Copyright (C) 2009 Marek Vasut + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MEDIA_OV96XX_H__ +#define __MEDIA_OV96XX_H__ + +/* Register definitions */ +#define OV96XX_GAIN 0x00 +#define OV96XX_BLUE 0x01 +#define OV96XX_RED 0x02 +#define OV96XX_VFER 0x03 +#define OV96XX_COM1 0x04 +#define OV96XX_BAVE 0x05 +#define OV96XX_GEAVE 0x06 +#define OV96XX_RSID 0x07 +#define OV96XX_RAVE 0x08 +#define OV96XX_COM2 0x09 +#define OV96XX_PID 0x0a +#define OV96XX_VER 0x0b +#define OV96XX_COM3 0x0c +#define OV96XX_COM4 0x0d +#define OV96XX_COM5 0x0e +#define OV96XX_COM6 0x0f +#define OV96XX_AECH 0x10 +#define OV96XX_CLKRC 0x11 +#define OV96XX_COM7 0x12 +#define OV96XX_COM8 0x13 +#define OV96XX_COM9 0x14 +#define OV96XX_COM10 0x15 +/* 0x16 - RESERVED */ +#define OV96XX_HSTART 0x17 +#define OV96XX_HSTOP 0x18 +#define OV96XX_VSTART 0x19 +#define OV96XX_VSTOP 0x1a +#define OV96XX_PSHFT 0x1b +#define OV96XX_MIDH 0x1c +#define OV96XX_MIDL 0x1d +#define OV96XX_MVFP 0x1e +#define OV96XX_LAEC 0x1f +#define OV96XX_BOS 0x20 +#define OV96XX_GBOS 0x21 +#define OV96XX_GROS 0x22 +#define OV96XX_ROS 0x23 +#define OV96XX_AEW 0x24 +#define OV96XX_AEB 0x25 +#define OV96XX_VPT 0x26 +#define OV96XX_BBIAS 0x27 +#define OV96XX_GBBIAS 0x28 +/* 0x29 - RESERVED */ +#define OV96XX_EXHCH 0x2a +#define OV96XX_EXHCL 0x2b +#define OV96XX_RBIAS 0x2c +#define OV96XX_ADVFL 0x2d +#define OV96XX_ADVFH 0x2e +#define OV96XX_YAVE 0x2f +#define OV96XX_HSYST 0x30 +#define OV96XX_HSYEN 0x31 +#define OV96XX_HREF 0x32 +#define OV96XX_CHLF 0x33 +#define OV96XX_ARBLM 0x34 +/* 0x35 - RESERVED */ +/* 0x36 - RESERVED */ +#define OV96XX_ADC 0x37 +#define OV96XX_ACOM 0x38 +#define OV96XX_OFON 0x39 +#define OV96XX_TSLB 0x3a +#define OV96XX_COM11 0x3b +#define OV96XX_COM12 0x3c +#define OV96XX_COM13 0x3d +#define OV96XX_COM14 0x3e +#define OV96XX_EDGE 0x3f +#define OV96XX_COM15 0x40 +#define OV96XX_COM16 0x41 +#define OV96XX_COM17 0x42 +/* 0x43 - RESERVED */ +/* 0x44 - RESERVED */ +/* 0x45 - RESERVED */ +/* 0x46 - RESERVED */ +/* 0x47 - RESERVED */ +/* 0x48 - RESERVED */ +/* 0x49 - RESERVED */ +/* 0x4a - RESERVED */ +/* 0x4b - RESERVED */ +/* 0x4c - RESERVED */ +/* 0x4d - RESERVED */ +/* 0x4e - RESERVED */ +#define OV96XX_MTX1 0x4f +#define OV96XX_MTX2 0x50 +#define OV96XX_MTX3 0x51 +#define OV96XX_MTX4 0x52 +#define OV96XX_MTX5 0x53 +#define OV96XX_MTX6 0x54 +#define OV96XX_MTX7 0x55 +#define OV96XX_MTX8 0x56 +#define OV96XX_MTX9 0x57 +#define OV96XX_MTXS 0x58 +/* 0x59 - RESERVED */ +/* 0x5a - RESERVED */ +/* 0x5b - RESERVED */ +/* 0x5c - RESERVED */ +/* 0x5d - RESERVED */ +/* 0x5e - RESERVED */ +/* 0x5f - RESERVED */ +/* 0x60 - RESERVED */ +/* 0x61 - RESERVED */ +#define OV96XX_LCC1 0x62 +#define OV96XX_LCC2 0x63 +#define OV96XX_LCC3 0x64 +#define OV96XX_LCC4 0x65 +#define OV96XX_LCC5 0x66 +#define OV96XX_MANU 0x67 +#define OV96XX_MANV 0x68 +#define OV96XX_HV 0x69 +#define OV96XX_MBD 0x6a +#define OV96XX_DBLV 0x6b +#define OV96XX_GSP 0x6c /* ... till 0x7b */ +#define OV96XX_GST 0x7c /* ... till 0x8a */ + +#define OV96XX_CLKRC_DPLL_EN 0x80 +#define OV96XX_CLKRC_DIRECT 0x40 +#define OV96XX_CLKRC_DIV(x) (x & 0x3f) + +#define OV96XX_PSHFT_VAL(x) (x & 0xff) + +#define OV96XX_ACOM_2X_ANALOG 0x80 +#define OV96XX_ACOM_RSVD 0x12 + +#define OV96XX_MVFP_V 0x10 +#define OV96XX_MVFP_H 0x20 + +#define OV96XX_COM1_HREF_NOSKIP 0x00 +#define OV96XX_COM1_HREF_2SKIP 0x04 +#define OV96XX_COM1_HREF_3SKIP 0x08 +#define OV96XX_COM1_QQFMT 0x20 + +#define OV96XX_COM2_SSM 0x10 + +#define OV96XX_COM3_VP 0x04 + +#define OV96XX_COM4_QQ_VP 0x80 +#define OV96XX_COM4_RSVD 0x40 + +#define OV96XX_COM5_SYSCLK 0x80 +#define OV96XX_COM5_LONGEXP 0x01 + +#define OV96XX_COM6_OPT_BLC 0x40 +#define OV96XX_COM6_ADBLC_BIAS 0x08 +#define OV96XX_COM6_FMT_RST 0x82 +#define OV96XX_COM6_ADBLC_OPTEN 0x01 + +#define OV96XX_COM7_RAW_RGB 0x01 +#define OV96XX_COM7_RGB 0x04 +#define OV96XX_COM7_QCIF 0x08 +#define OV96XX_COM7_QVGA 0x10 +#define OV96XX_COM7_CIF 0x20 +#define OV96XX_COM7_VGA 0x40 +#define OV96XX_COM7_SCCB_RESET 0x80 + +#define OV96XX_COM12_YUV_AVG 0x04 +#define OV96XX_COM12_RSVD 0x40 + +#define OV96XX_COM13_GAMMA_NONE 0x00 +#define OV96XX_COM13_GAMMA_Y 0x40 +#define OV96XX_COM13_GAMMA_RAW 0x80 +#define OV96XX_COM13_RGB_AVG 0x20 +#define OV96XX_COM13_MATRIX_EN 0x10 +#define OV96XX_COM13_Y_DELAY_EN 0x08 +#define OV96XX_COM13_YUV_DLY(x) (x & 0x07) + +#define OV96XX_COM15_OR_00FF 0x00 +#define OV96XX_COM15_OR_01FE 0x40 +#define OV96XX_COM15_OR_10F0 0xc0 +#define OV96XX_COM15_RGB_NORM 0x00 +#define OV96XX_COM15_RGB_565 0x10 +#define OV96XX_COM15_RGB_555 0x30 + +#define OV96XX_COM16_RB_AVG 0x01 + +/* IDs */ +#define OV9640_V2 0x9648 +#define OV9640_V3 0x9649 +#define OV9650 0x9652 +#define VERSION(pid, ver) ((pid<<8)|(ver&0xFF)) + +/* supported resolutions */ +enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA }; +const struct { + int width; + int height; +} ov96xx_resolutions[] = { + { 88, 72 }, /* QQCIF */ + { 160, 120 }, /* QQVGA */ + { 176, 144 }, /* QCIF */ + { 320, 240 }, /* QVGA */ + { 352, 288 }, /* CIF */ + { 640, 480 }, /* VGA */ + { 1280, 960 }, /* SXGA */ +}; + +/* Misc. structures */ +struct ov96xx_reg_alt { + u8 com7; + u8 com12; + u8 com13; + u8 com15; +}; + +struct ov96xx_reg { + u8 reg; + u8 val; +}; + +/* default register setup */ +const struct ov96xx_reg ov96xx_regs_dflt[] = { + { OV96XX_COM5, OV96XX_COM5_SYSCLK | OV96XX_COM5_LONGEXP }, + { OV96XX_COM6, OV96XX_COM6_OPT_BLC | OV96XX_COM6_ADBLC_BIAS | + OV96XX_COM6_FMT_RST | OV96XX_COM6_ADBLC_OPTEN }, + { OV96XX_PSHFT, OV96XX_PSHFT_VAL(0x01) }, + { OV96XX_ACOM, OV96XX_ACOM_2X_ANALOG | OV96XX_ACOM_RSVD }, + { OV96XX_COM16, OV96XX_COM16_RB_AVG }, + + /* Gamma curve P */ + { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 }, + { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 }, + { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 }, + { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 }, + + /* Gamma curve T */ + { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 }, + { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 }, + { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e }, + { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 }, +}; + +/* Configurations + * NOTE: for YUV, alter the following registers: + * COM12 |= OV96XX_COM12_YUV_AVG + * + * for RGB, alter the following registers: + * COM7 |= OV96XX_COM7_RGB + * COM13 |= OV96XX_COM13_RGB_AVG + * COM15 |= proper RGB color encoding mode + */ +const struct ov96xx_reg ov96xx_regs_qqcif[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x0f) }, + { OV96XX_COM1, OV96XX_COM1_QQFMT | OV96XX_COM1_HREF_2SKIP }, + { OV96XX_COM4, OV96XX_COM4_QQ_VP | OV96XX_COM4_RSVD }, + { OV96XX_COM7, OV96XX_COM7_QCIF }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_qqvga[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x07) }, + { OV96XX_COM1, OV96XX_COM1_QQFMT | OV96XX_COM1_HREF_2SKIP }, + { OV96XX_COM4, OV96XX_COM4_QQ_VP | OV96XX_COM4_RSVD }, + { OV96XX_COM7, OV96XX_COM7_QVGA }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_qcif[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x07) }, + { OV96XX_COM4, OV96XX_COM4_QQ_VP | OV96XX_COM4_RSVD }, + { OV96XX_COM7, OV96XX_COM7_QCIF }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_qvga[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x03) }, + { OV96XX_COM4, OV96XX_COM4_QQ_VP | OV96XX_COM4_RSVD }, + { OV96XX_COM7, OV96XX_COM7_QVGA }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_cif[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x03) }, + { OV96XX_COM3, OV96XX_COM3_VP }, + { OV96XX_COM7, OV96XX_COM7_CIF }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_vga[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x01) }, + { OV96XX_COM3, OV96XX_COM3_VP }, + { OV96XX_COM7, OV96XX_COM7_VGA }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_sxga[] = { + { OV96XX_CLKRC, OV96XX_CLKRC_DPLL_EN | OV96XX_CLKRC_DIV(0x01) }, + { OV96XX_COM3, OV96XX_COM3_VP }, + { OV96XX_COM7, 0 }, + { OV96XX_COM12, OV96XX_COM12_RSVD }, + { OV96XX_COM13, OV96XX_COM13_GAMMA_RAW | OV96XX_COM13_MATRIX_EN }, + { OV96XX_COM15, OV96XX_COM15_OR_10F0 }, +}; + +const struct ov96xx_reg ov96xx_regs_yuv[] = { + { OV96XX_MTX1, 0x50 }, + { OV96XX_MTX2, 0x43 }, + { OV96XX_MTX3, 0x0d }, + { OV96XX_MTX4, 0x19 }, + { OV96XX_MTX5, 0x4c }, + { OV96XX_MTX6, 0x65 }, + { OV96XX_MTX7, 0x40 }, + { OV96XX_MTX8, 0x40 }, + { OV96XX_MTX9, 0x40 }, + { OV96XX_MTXS, 0x0f }, +}; + +const struct ov96xx_reg ov96xx_regs_rgb[] = { + { OV96XX_MTX1, 0x71 }, + { OV96XX_MTX2, 0x3e }, + { OV96XX_MTX3, 0x0c }, + { OV96XX_MTX4, 0x33 }, + { OV96XX_MTX5, 0x72 }, + { OV96XX_MTX6, 0x00 }, + { OV96XX_MTX7, 0x2b }, + { OV96XX_MTX8, 0x66 }, + { OV96XX_MTX9, 0xd2 }, + { OV96XX_MTXS, 0x65 }, +}; + +struct ov96xx_priv { + struct soc_camera_device icd; + struct soc_camera_link *link; + struct i2c_client *client; + + int model; + int revision; + + bool flag_vflip; + bool flag_hflip; +}; + +/* NOTE: The RGB555X format still has issues, so it's left out. */ +static const struct soc_camera_data_format ov96xx_fmt_lists[] = { +{ + .name = "VYUY", + .fourcc = V4L2_PIX_FMT_VYUY, + .depth = 16, + .colorspace = V4L2_COLORSPACE_JPEG, +}, +{ + .name = "RGB565X", + .fourcc = V4L2_PIX_FMT_RGB565X, + .depth = 16, + .colorspace = V4L2_COLORSPACE_SRGB, +} +}; + +static const struct v4l2_queryctrl ov96xx_controls[] = { + { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip Vertically", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip Horizontally", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, +}; + + +#endif /* __OV96XX_H__ */ diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h index 4d7e227..c7e68d3 100644 --- a/include/media/v4l2-chip-ident.h +++ b/include/media/v4l2-chip-ident.h @@ -60,6 +60,8 @@ enum { V4L2_IDENT_OV7670 = 250, V4L2_IDENT_OV7720 = 251, V4L2_IDENT_OV7725 = 252, + V4L2_IDENT_OV9640 = 253, + V4L2_IDENT_OV9650 = 254, /* module saa7146: reserved range 300-309 */ V4L2_IDENT_SAA7146 = 300, -- 1.6.3.3